Memory circuits can contain defective (i.e., faulty) memory cells. Built-in self-test (BIST) and built-in self-repair (BISR) routines are performed to determine the faulty memory cells and substitute redundant functional memory cells for the defective memory cells. During a BIST and BISR (BIST/BISR) routine, a device where the memory circuit is implemented determines a row containing one or more faulty memory cells via a self-diagnostic routine and implements address mapping logic to substitute a functional row for the defective row. Hard BISR routines are configured to burn the functional addresses via fuses in a fuse box (or bank) that is implemented in the device. A hard BISR operation mode is configured to load memory repair information directly from the fuse box into memory registers. The memory is remapped to functional locations without re-running the BIST routine.
The steps of the hard BISR routine are as follows:
1. During a wafer sort testing process during chip manufacture, the BIST/BISR routine is performed on the device to (i) determine the repair solution for the memory and (ii) scan out the repair solution. A test access port (TAP) controller is programmed to assert the relevant commands to a BISR wrapper. However, clocks for the TAP control and the BISR wrapper are different. The hardware (i.e., on silicon) implementation of the repair solution has additional clocking parameters. The BISR clocking is implemented via one or more global registers to synchronize test hardware and test patterns.
2. The memory repair solution is programmed on the die via laser blown fuses.
3. At final test and in the field, the memory repair data from the fuses is scanned into the memory after which the repaired memory is functional.
The steps 1 and 3 are implemented having a specific number of clock cycle counts. Any clock cycle mismatch can result in incorrect memory address values being scanned out during manufacture or scanned in during field operation.
During step 1, the TAP controller scans out the repair solution. The conversion of the scanned out information (i.e., the repair solution) into fuses to be blown is based on the clock cycle count. However, the TAP clock has a different timing from the BISR clock. Furthermore, even when operating in response to the same clock signal, different memory blocks on the chip each implement a different specific number of clock cycles to be applied after which the clocking is configured to stop. Conventional memories are implemented having user (i.e., designer) calculated differences between the TAP clock and the system (i.e., memory) clock. A routine is implemented by the designer and/or user to exercise the repair solutions with the appropriate calculated number of clock cycles.
Conventional approaches fail to provide a standard solution for power-up in hard BISR memories. Conventional approaches define general test requirements and depend on the design engineer and/or customer to determine specific implementation parameters (i.e., clock cycle counts).
Conventional approaches have one or more of the following deficiencies: (i) difficulty in test pattern generation and design debug which can cause extended development cycle time during prototyping, (ii) difficulty in generating test patterns to meet the exact cycle count for scan (i.e., to scan out the repair information when the BIST/BISR routine is performed) during power-up, and/or (iii) long development and test times for prototype circuits.
It would be desirable to have a method and/or architecture for memory circuit BISR that (i) provides a standard BISR implementation for a variety of memories, (ii) eliminates user calculation of test and memory clock cycle differences, (iii) reduces prototype development time and cost, (iv) simplifies user memory implementation, and/or (v) simplifies test pattern generation.